Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
Although the need for increased communication bandwidth continues to drive future designs, support for the lower bandwidth legacy systems is needed. As such, the future designs are required to provide a wide range of scalability, whereby data rate, slew rate, and many other physical (PHY) layer attributes are adaptable. For example, a particular transmitter/receiver (TX/RX) pair may be configured for use as both a high-definition serial digital interface (HD-SDI) and a standard-definition serial digital interface (SD-SDI). Both standards have similar specifications, but differ from each other at the PHY layer with respect to, for example, bit rate and edge rate. In order to provide a cost effective solution for both interfaces, the same transmitter/receiver pair may be required to adapt to both specifications by changing its mode of operation.
The bit rate, for example, of the PHY layer may determine the particular mode of operation that is implemented by each transceiver. To maintain phase/frequency coherency, each transceiver may employ a phase locked loop (PLL), whereby the PLL phase and frequency aligns a locally generated clock, e.g., a voltage controlled oscillator (VCO), to an external reference clock or data signal.
In order to achieve a phase/frequency locked state in a shorter amount of time, a conventional frequency calibration process may be employed. In particular, the VCO's output frequency is programmed, prior to closing the PLL's control loop, to be within a programmable frequency range of the reference clock frequency or data signal frequency. Conventionally, a frequency detection circuit has been employed to determine a coarse frequency relationship between the VCO output frequency and the reference clock frequency, i.e., whether the two clock frequencies are within a predetermined frequency range of one another and which of the two signals is operating at a frequency higher than the other. Such an arrangement is disclosed in Bataineh et al., U.S. patent application Ser. No. 11/035,773 filed Jan. 14, 2005, and is incorporated herein by reference in its entirety
The coarse frequency relationship is then utilized by a conventional calibration circuit, whereby a fixed frequency step size is used to increase or decrease the output frequency of the VCO. The frequency detection circuit is then used to determine when the relationship between the VCO frequency and the reference frequency has changed, i.e., when the VCO frequency relative to the reference frequency has transitioned from higher to lower, or from lower to higher.
Several disadvantages exist, however, when calibration of the VCO frequency is performed using a fixed frequency step size. First, if the frequency difference between the VCO frequency and the reference frequency is large, then a proportional amount of time is required to step the VCO frequency to within the predetermined frequency range of the reference frequency. Second, if a large frequency step size is used, time may be wasted by continuously undershooting and overshooting the predetermined frequency range by under-stepping or over-stepping the VCO frequency. Third, if the VCO frequency begins at a frequency that is relatively close to the reference frequency, then applying a large frequency step size may actually tune the VCO frequency even further away from the reference frequency.
Accordingly, advanced calibration methods continue to be developed to further decrease the amount of time required to obtain frequency/phase coherency with a reference frequency. Such an advanced calibration method would be particularly useful in programmable, multi-frequency capable circuits, such as programmable logic devices (PLDs), that utilize programmable serial communication transceivers over a wide frequency range of operation.